SERIAL DIAGNOSTIC FAULT SIMULATION FOR SYNCHRONOUS SEQUENTIAL-CIRCUITS

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is presented. A two level optimization techniq ue has been developed and used to prompt the processing speed. In the high level, an efficient list, which stores the indistinguishable faul ts, for each fault during the diagnostic fault simulation, and the lis t maintaining algorithm are applied. Thus the number of fault-pair out put response comparisons among all the faults is minimized. In the low level, a bit-parallel comparison is developed to speed up the compari son process. Therefore, the different diagnostic measure reports for a given test set can be generated very quickly. In addition, the simula tor is extended to diagnose the single stuck-at device fault. Experime ntal results show that this diagnostic fault simulator achieves a sign ificant speedup compared to previous methods.