SCHEDULING WITH MULTIPLE VOLTAGES

This paper presents a low power design technique at the behavioral syn thesis stage. A scheduling technique for low power is studied and a th eoretical foundation is established. The equation for dynamic power, P -dyn=V(dd)(2)C(load)f(switch), is used as a basis. The voltage applied to the functional units is varied, slowing down the functional unit t hroughput and reducing the power while meeting the throughput constrai nt for the entire system. The input to our problem is an unscheduled d ata flow graph with a timing constraint. The goal is to establish a vo ltage value at which each of the operations of the data flow graph wou ld be performed, thereby fixing the latency for the operation such tha t the total timing constraint for the system is met. We give an algori thm to minimize the system's power; the algorithm finds an optimal sch edule. The timing constraint for our system could be any value greater than or equal to the critical path. The experimental results for some high-level synthesis benchmarks show considerable reduction in the po wer consumption. Using 5 and 3 V supply voltages we achieve a maximum reduction of approximately 40% given tight timing constraints. Similar ly, we obtain a 46% reduction using 5, 3 and 2.4 V supply voltages. Fo r larger timing constraints, the maximum reduction is about 64% using 5 and 3 V supply voltages and a maximum reduction of about 74% using 5 , 3 and 2.4 V supply voltages.