A NEW APPROACH FOR THE DESIGN OF LINEAR SYSTOLIC ARRAYS FOR COMPUTING3RD-ORDER CUMULANTS

VLSI architectures for computing higher-order cumulants have gained co nsiderable attention recently, as a consequence of the increasingly ev ident importance of using cumulant functions as an effective signal pr ocessing tool. This paper presents a new approach for designing linear systolic arrays for computing third-order cumulants. First, the estim ation of third-order cumulants is formulated elegantly as a sequence o f matrix multiplication operations. Then a special structure systolic array for this matrix multiplication is developed. The resulting struc ture is an efficient unidirectional array which not only is adequate f or VLSI implementations but also is suitable for supporting fault-tole rance techniques.