SCALABLE PARALLEL PROCESSOR ARRAY FOR JACOBI-TYPE MATRIX COMPUTATIONS

Citation
Hw. Vandijk et al., SCALABLE PARALLEL PROCESSOR ARRAY FOR JACOBI-TYPE MATRIX COMPUTATIONS, Integration, 20(1), 1995, pp. 41-61
Citations number
18
Categorie Soggetti
System Science","Computer Sciences","Computer Science Hardware & Architecture
Journal title
ISSN journal
01679260
Volume
20
Issue
1
Year of publication
1995
Pages
41 - 61
Database
ISI
SICI code
0167-9260(1995)20:1<41:SPPAFJ>2.0.ZU;2-K
Abstract
This paper addresses the problem of designing a family of potential pr ocessor arrays for the execution of the so-called Jacobi algorithms. I t extends the more familiar problem of designing a single fixed-size p rocessor array for a particular program and it is parametrised with re spect to size in two ways. Firstly, the program is no longer a particu lar one but is a member from a set of related programs. Secondly, the processor array itself is now also parametrised with respect to its di mension and size. There are thus three parameters involved, one to ide ntify the program, one to select the program's size and one for the po ssible dimensions/sizes of the array implementation. The approach prop osed in this paper is to use the design model and methods which have b een used so far for the 'one array for one program' design problem and provide - instead of a processor array - a parameter controlled gener ic processor and a program to generate the control for the execution o f a selected program on a specific array of such processors. This allo ws a user to compose an array out of a number of these generic process ors and generate the necessary control signals actually executing the selected program. The control signals propagate down the array and ins truct each processor how to process the incoming data. The control is hierarchical in the sense that a processor decodes and processes the i ncoming control signals so as to fix internal behaviour. The more proc essors are used, the less sequential the execution of the program will be. The generic processor uses Cordic arithmetic for its processing p art and in addition to this it consists of a communication part and an internal memory bank. Communication between processors is a-synchrono us while the internal timing is clocked.