LITHOGRAPHY AND FABRICATION PROCESSES FOR SUB-100 NM SCALE COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR

We explore the fabrication of complementary metal-oxide-semiconductor (CMOS) devices and circuits with a critical dimension of 100 nm and be low using a variety of lithographic, processing. materials, and device design innovations. Device design parameters tailored for high perfor mance al low operating power include the use of bulk and silicon-on-in sulator substrates, a steep retrograde channel doping: scheme, ultrath in (similar to 3 nm) gate dielectric, shallow source, and drain extens ions, and a metal-over-gate structure. Mix-and-match lithography, incl uding the use of electron-beam lithography for all critical levels, x- ray lithography for gate level definition, and optical (deep ultraviol et) litography for noncritical levels, is used in an effort to exploit the strongest features of each of these lithography technologies. New reactive ion etching processes for CMOS gate definition as well as fo r device and circuit metallization have been developed in conjunction with the litographic processes in an effort to facilitate the scaling of silicon devices toward their ultimate limits. (C) 1995 American Vac uum Society.