INTEGRATION OF SOL-GEL PZT WITH SILICON-ON-SAPPHIRE CMOS CIRCUITRY

Authors
BLAND T OBHI J PATEL A KIRBY P ROBINSON M KERR J
Citation
T. Bland et al., INTEGRATION OF SOL-GEL PZT WITH SILICON-ON-SAPPHIRE CMOS CIRCUITRY, Microelectronic engineering, 29(1-4), 1995, pp. 29-32
Citations number
3
Categorie Soggetti
Optics,"Physics, Applied","Engineering, Eletrical & Electronic
Journal title
Microelectronic engineering → ACNP
ISSN journal
01679317
Volume
29
Issue
1-4
Year of publication
1995
Pages
29 - 32
Database
ISI
SICI code
0167-9317(1995)29:1-4<29:IOSPWS>2.0.ZU;2-U
Abstract
Deposition and patterning processes to produce 9x9 mu m ferroelectric capacitor (FECAP) structures, and the back-end processes necessary to integrate them with silicon-on-sapphire (SOS) circuits have been devel oped with the aim of demonstrating a 4kbit non-volatile RAM (NVRAM) on SOS. PZT thin film deposition by a sol-gel route has been characteris ed and dielectric, ferroelectric and fatigue measurements taken.