MULTILAYER RESIST PROCESS FOR ASYMMETRIC GATE RECESS IN FIELD-EFFECT TRANSISTORS

A multilayer electron beam resist process for asymmetric gate recess f or field-effect transistors (FETs) in compound semiconductors is prese nted. With this process, it is possible to decrease the drain conducta nce while maintaining a large source conductance by recessing the high ly doped cap of the FET structure to a greater extent in the direction of the drain. This can be accomplished with a single electron-beam ex posure process followed by a single step development due to the differ ent sensitivities of the resist layers. A weak sidelobe exposure on th e drain side of the gate is also needed during the electron-beam expos ure process. This resist process is designed to reduce the number of l ithography steps and the critical alignment required in the convention al ''double-gate recess'' process. InAlAS/In0.7Ga0.3As modulation-dope d field-effect transistors (MODFETs) fabricated using the new process were found to have gate-to-drain breakdown voltages of 8.5 V, which wa s a significant improvement over the 2.25 V gate-to-drain breakdown vo ltages of the MODFETs fabricated using a conventional symmetric T-gate process.