COMPARISON OF GATE-EDGE EFFECTS ON THE HOT-CARRIER-INDUCED DEGRADATION OF LDD N-CHANNEL AND P-CHANNEL MOSFETS

The gate-to-drain overlap is very important for MOSFET performances an d reliabilities. We present a comparative study of the gate-edge effec ts on the hot-carrier induced degradation of submicron LDD n- and p-ch annel MOSFETs. Three different structures: (1) the reentrant poly gate , (2) the graded-gate-oxide and (3) the well overlapped gate and drain , are investigated. For n-MOSFETs, both graded-gate-oxide structures a nd reentrant poly gates reduce the gate-to-LDD overlap and result in a high degradation rate in the linear drain current. The maximum transc onductance degradation for the graded-gate-oxide structures, however, is very close to the well overlapped devices. In contrast to the n-MOS FET cases, we observed for the first time that p-MOSFETs with weakly o verlapped gate and drain result in a lower degradation rate and a long er device lifetime than that with well overlapped ones. Our work sugge sts that n- and p-channel LDDs must be designed in a different manner in order to minimize the hot-carrier induced degradation.