ADVANCED APPLICATION OF HIERARCHY REORGANIZATION IN E-BEAM LITHOGRAPHY

The E-beam proximity effect correction (PEG) of very large layouts is still regarded a very difficult step during data preparation. The CPU- time for today's integrated circuits extends into weeks, file sizes in to Gigabytes. Recently, Sigma-C achieved a breakthrough in handling me mory chips by developing a general approach for hierarchical data prep aration. A very important achievement is the hierarchy reorganisation, which enables the correction of chips like the 256 Mb. In this paper the further development, needed to extend the theory to logic devices, to innovate the PEC of random layouts, will be presented. First resul ts of the correction of logics will be demonstrated in comparison to f lat processing.