BILAYER RESIST PROCESS FOR EXPOSURE WITH LOW-VOLTAGE ELECTRONS (STM-LITHOGRAPHY)

Citation
R. Leuschner et al., BILAYER RESIST PROCESS FOR EXPOSURE WITH LOW-VOLTAGE ELECTRONS (STM-LITHOGRAPHY), Microelectronic engineering, 30(1-4), 1996, pp. 447-450
Citations number
10
Categorie Soggetti
Optics,"Physics, Applied","Engineering, Eletrical & Electronic
Journal title
ISSN journal
01679317
Volume
30
Issue
1-4
Year of publication
1996
Pages
447 - 450
Database
ISI
SICI code
0167-9317(1996)30:1-4<447:BRPFEW>2.0.ZU;2-4
Abstract
With STM lithography employing a bilayer resist system, an electron se nsitive top resist and a conductive bottom resist, it is possible to g enerate patterns with dimensions of 100 nm and less. Patterns with asp ect ratios up to 8 at a width of 50 nm in flat silicon oxide surface h ave been achieved. We also demonstrate, that it is possible to operate on prepatterned substrates using a third planarizing resist layer. Th e exposure mechanism in our CARL top resist has been determined to wor k differently from the mechanism in the high electron energy regime. T he low energy electrons directly cleave the t-butyl ester group. Chemi cal amplification was not observed. The maximum writing speed for comp lete exposure in the resist was 1-5 mu m/s at 20 pA writing current.