A NEW APPLICATION-SPECIFIC FIB SYSTEM ARCHITECTURE

Time-to-market is a key factor that often determines the economic succ ess or failure of new integrated circuit designs. The key being that t he first company to market a new IC commands a substantial price margi n before competitors release their products. Any tool that can reduce the debug and verification time for new designs provides an important competitive advantage. FIB ''Cut & Paste'' systems and electron beam p robers are two such tools whose importance is increasing as IC design rules shrink below 0.5 mu m. Little attempt, so far, has been made to exploit directly the synergy between these two technologies and thereb y streamline still further IC debug and verification. A new FIB system is presented. The architecture is designed to take advantage of the s ynergy between e-beam and FIB technologies. The goal is to minimize di agnosis cycle time and thereby improve overall engineering productivit y.