A CMOS IC FOR GB S VITERBI DECODING - SYSTEM-DESIGN AND VLSI IMPLEMENTATION/

At present, the Viterbi algorithm (VA) is widely used in communication systems for decoding and equalization, The achievable speed of conven tional Viterbi decoders (VD's) is limited by the inherent nonlinear ad d-compare-select (ACS) recursion, The aim of this paper is to describe system design and VLSI implementation of a complex system of fabricat ed ASIC's for high speed Viterbi decoding using the ''minimized method '' (MM) parallelized VA. We particularly emphasize the interaction bet ween system design, architecture and VLSI implementation as well as sy stem partitioning issues and the resulting requirements for the system design flow, Our design objectives were 1) to achieve the same decodi ng performance as a conventional VD using the parallelized algorithm, 2) to achieve a speed of more than 1 Gb/s, and 3) to realize a system for this task using a single cascadable ASIC, With a minimum system co nfiguration of four identical ASIC's produced by using 1.0 mu CMOS tec hnology, the design objective of a decoding speed of 1.2 Gb/s is achie ved, This means, compared to previous implementations of Viterbi decod ers, the speed is increased by an order of magnitude.