PREDICTIVE SYSTEM SHUTDOWN AND OTHER ARCHITECTURAL TECHNIQUES FOR ENERGY-EFFICIENT PROGRAMMABLE COMPUTATION

With the popularity of portable devices such as personal digital assis tants and personal communicators, as well as with increasing awareness of the economic and environmental costs of power consumption by deskt op computers, energy efficiency has emerged as an important issue in t he design of electronic systems, While power efficient ASIC's with ded icated architectures have addressed the energy efficiency issue for ni che applications such as DSP, much of the computation continues to be implemented as software running on programmable processors such as mic roprocessors, microcontrollers, and programmable DSP's, Not only is th is true for general purpose computation on personal computers and work stations, but also for portable devices, application-specific systems etc, In fact, firmware and embedded software executing on RISC and DSP processor cores that are embedded in ASIC's has emerged as a leading implementation methodology for speech coding, modem functionality, vid eo compression, communication protocol processing etc, This paper desc ribes architectural techniques for energy efficient implementation of programmable computation, particularly focussing on the computation ne eded in portable devices where event-driven user interfaces, communica tion protocols, and signal processing play a dominant role, Two key ap proaches described here are predictive system shutdown and extended vo ltage scaling, Results indicate that a large reduction in power consum ption can be achieved over current day solutions with little or no los s in system performance.