AN EVALUATION OF ASYNCHRONOUS ADDITION

There is considerable interest at present in the design of asynchronou s systems based on the use of self-timing components for arithmetic an d other operations. Amongst the advantages claimed for asynchronous de sign are ease of design, high speed, low power, and device speed indep endence. An often quoted example of the speed improvement possible fro m self-timed hardware is parallel binary addition, where the carry sig nals in the worst case must propagate through n stages before the sum can be guaranteed correct. In practice, however, it is not possible to achieve significant speed advantage from the method, and this paper s hows that asynchronous adders only give a performance improvement over more conventional hardware in very limited conditions, where the size and regularity of the layout are at a premium.