A GBIT-SCALE DRAM STACKED CAPACITOR WITH ECR MOCVD SRTIO3 OVER RIE PATTERNED RUO2 TIN STORAGE NODES/

The capacitor requirements for Gbit-scale DRAMs are discussed in detai l. The choice of SrTiO3 thin films over a stacked RuO2/TiN structure f or the 1 Gbit DRAM is explained, and particular emphasis is put on the necessity of a stacked capacitor structure and on the selection of a suitable electrode material. The influence of film composition, film t hickness and substrate temperature on the properties of ECR MOCVD SrTi O3 films is then presented. Maximum permittivity and low leakage curre nt density were obtained for stoichiometric composition, Sr/Ti = 1.0. A thickness of at least 400 Angstrom was found to be necessary to obta in SrTiO3 films with sufficient electrical properties. A substrate tem perature of 450 degrees C was found to be a suitable temperature for d irect deposition of crystallized SrTiO3 and no degradation of the RuO2 /TiN bottom electrode structure. A new reactive ion etching process wa s developed to pattern RuO2/TiN nodes. The key characteristics of this process are the use of an SOG mask, the choice of an O-2/Cl-2 gas mix ture which allows reactive etching of RuO2 at a high rate of 2500 Angs trom/min and with a RuO2/SOG selectivity more than 10:1, and an O-2 as hing treatment performed at 150 degrees C at the end of the etching pr ocess, which helps remove the damaged layer observed at the RuO2 surfa ce after RuO2/TiN etching. A new stacked capacitor technology comprisi ng reactive ion etching of RuO2/TiN storage nodes and low temperature deposition of SrTiO3 thin films by ECR MOCVD at 450 degrees C was succ essfully developed. A storage capacitance of 25 fF and a leakage curre nt density of 8 x 10(-7) A/cm(2) can be obtained at half V-cc = +1.0 V , for SrTiO3 films with a sidewall thickness of 400 Angstrom deposited on 0.5 mu m stacked RuO2/TiN storage nodes. This capacitor technology is suitable for use in Gbit-scale DRAMs.