INTEGRATION OF BST THIN-FILM FOR DRAM FABRICATION

A process technique to integrate the sputter-deposited BST thin film i nto the DRAM is discussed. With some reconsiderations concerning the g rain structure of the BST, the care of the electrode edge, the thermal stability of the capacitor characteristic, the upper dielectric of th e capacitor and so on, the BST was successfully integrated into a capa citor TEG structure on a 9Mbits scale. By using the newly developed in tegration technique, a 4MDRAM was fabricated, exhibiting the normal bi t function with a wide margin. After this, improvements on the thermal stability are needed by developing a barrier layer under the bottom P t electrode that is more heat-resistant than currently achieved.