ANALYSIS OF LATCHUP SUSCEPTIBILITY TO INTERNAL LOGICAL STATES BY USING A LASER-BEAM

Experimental results using a laser beam in order to demonstrate the de pendence of the latchup sensitivity versus internal logical states are presented. The latch-up triggering mechanisms involved by this method are then numerically analysed by the means of a 2D device simulator i n a mixed mode environment. We show that the susceptibility to the lat chup phenomenon is increased when the MOS transistor concerned by the parasitic structure is in its low impedance state. It also demonstrate s that the usual precautions taken in order to prevent the latchup phe nomenon may be efficiently put to the test by using a laser beam conta ctless testing technique.