This paper presents a new tool set called LayDis providing advanced na
vigation support for chipinternal probing. Although the tool set has b
een designed primarily for electron beam test equipment (EBT), it is e
xtendable to support optical beam test equipment, contacting prober st
ations, focused ion beam stations (FIB), or laser cutters. The new nav
igation system has got multiple links to the CAD-data, and its main ad
vantage comes from the fact that layout navigation can be performed ev
en if nothing else but layout data (GDS II file) is available. The use
r is guided by the system through all stages of pre-processing the des
ign data. The software has built-in features for automatic probing poi
nt selection based on technology-proprietary selection rules. An uniqu
e built-in feature is the full support of layout navigation based on t
ext information contained in a layout file. To support complete netlis
t-driven navigation for fault localisation purposes a pre-processor is
available to use Dracula LVS results for the crossmapping of netlist
naming information and layout polygon description. In addition, LayDis
is capable of generating and processing probing point list files for
the repeated operation of the same verification and measurement tasks.
This feature enables the Design&Test engineer to verify or characteri
se several identical devices during the process of 'First Silicon char
acterisation'.