ON THE LOWER BOUNDS OF CMOS SUPPLY VOLTAGE

The lower bounds of the supply voltage V-DD of ultra-low-power CMOS te chnologies are investigated under the constraints of standard digital circuit design. After discussing the peculiarities of ultra-low-power CMOS processes, low-voltage device operation, and scaling benefits, th e lower limits for V-DD are narrowed down from two sides. First, a sim ple inverter based on idealised transistors is investigated analytical ly to determine a set of absolute lower bounds of V-DD, for a set of g iven design constraints, i.e. minimum gain and noise margins. Next, th e feasibility and performance of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-pr ocessing of the simulated I-V and capacitance data, to determine a set of achievable lower bounds of V-DD. On the basis of state-of-the-art processes and special scaling, a set of possible ultra-low-power CMOS processes was developed and numerically analysed on the gate level. Th ese numerical data are then related to the analytical results.