MODELING AND APPLICATION OF FULLY DEPLETED SOI MOSFETS FOR LOW-VOLTAGE, LOW-POWER ANALOG CMOS CIRCUITS

Transistor models which reproduce the superior device characteristics of fully depleted silicon-on-insulator (SOI) MOSFETs and which are eff icient for the design of analogue CMOS circuits are discussed and vali dated. These analogue models are then used to investigate the signific ant performance improvement that several basic analogue cells can achi eve when optimized in fully depleted SOI CMOS, rather than in bulk CMO S technology. Experimental verifications support this original demonst ration of the great potential of fully depleted SOI CMOS for low volta ge, low power analogue applications.