CMOS DEVICE AND INTERCONNECT TECHNOLOGY ENHANCEMENTS FOR LOW-POWER LOW-VOLTAGE APPLICATIONS

This paper reviews current advances and future directions in the devel opment of scaled CMOS device technologies on bulk and SOI substrates, acid multilevel interconnect architectures for application to low powe r/low voltage ULSI. Although traditional device scaling (as per the SI A roadmap) calls for the concomitant reduction in device sizes and pow er supplies driven by DRAM technology generations, the achievement of ultra-low power dissipation (at V-dd approximate to 1 V or less) and h igh speed performance (for battery operated portable systems) will acc elerate scaling and drive several new engineered structures, such as v ertically modulated channel doping profiles, ultra-shallow source/drai n junctions and ultra-thin SOI devices that are tailored for low volta ges. In addition, the development of novel low temperature processing schemes, such as Damascene, will be accelerated for integrating low K dielectrics with Al or Cu metallizations for multilevel interconnect a rchitectures that are designed for low power. The successful incorpora tion of these technologies into portable electronics systems of the co ming decade will require meeting the timing, manufacturability, cost a nd performance goals, in concert with the SIA roadmap.