A DISCRETE FORMALIZATION OF SWITCH-LEVEL CIRCUIT BEHAVIOR

In [1], we developed a discrete switch-level circuit model for digital CMOS circuits. It describes the logic behavior static as well as dyna mic - of abstract transistor networks and captures logic faults due to conflicts, nondefined gates, hazards, charge sharing, imperfectness o f switches, and relative timing problems. Although the model is direct ed towards CMOS, it is applicable to every FET technology. It offers a straightforward description of switch-level circuit behavior and a ri gorous mathematical framework with which powerful results can be infer red. Due to a stepwise refinement of a basic model, we are able to kee p grip on the formalization, can consider each important physical aspe ct in isolation, and, moreover, can formally compare the notions in th e refined models with their counterparts in the basic model. The overv iew given in this paper concentrates on the main issues of the model, and discusses the major results. For a more detailed discussion of the model, a more detailed motivation of the choices made, and proofs of the results obtained, we refer to [1].(2)