DETERMINATION OF LDD MOSFET DRAIN RESISTANCE FROM DEVICE SIMULATION

A simple, efficient and accurate technique for the determination of th e drain resistance of LDD MOSFETs, using a two-dimensional device simu lator, is presented. This method does not require the artificial intro duction of constraints that would alter the normal operating condition s and geometry of the device. Comparison is made with a more elaborate technique, where the drain region is modelled as a network of resista nces. For an appropriately chosen mesh size, good agreement to within 10% has been achieved for the two techniques. In terms of computationa l labour, the simple technique enjoys at least an order of magnitude a dvantage compared with the more elaborate model. The two techniques ha ve also been used to study the dependence of the drain resistance on t he gate and the drain bias, and to establish the accuracy over a broad bias range. An estimate is also made of the degradation of the drain resistance due to hot-carrier stress.