A PIXEL SIZE SHRINKAGE OF AMPLIFIED MOS IMAGER WITH 2-LINE MIXING

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing an d high sensitivity. A 1/4-in format 250-k pixel image sensor was devel oped using a 0.8-mu m CMOS process, The difference from the convention al CMOS process is an additional layer of ion-implantation process, Th e power supply voltages of this imager are 4 and 6 V. The dynamic rang e of 75 dB, the sensitivity of 1.8 mu A/lx, and the smear noise of les s than -120 dB have been attained for the pixel size of 7.2 (H) x 5.6 (V) mu m(2). Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively.