ENHANCED CAD MODEL FOR GATE LEAKAGE CURRENT IN HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS

Citation
Ky. Lee et al., ENHANCED CAD MODEL FOR GATE LEAKAGE CURRENT IN HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS, I.E.E.E. transactions on electron devices, 43(6), 1996, pp. 845-851
Citations number
16
Categorie Soggetti
Engineering, Eletrical & Electronic","Physics, Applied
ISSN journal
00189383
Volume
43
Issue
6
Year of publication
1996
Pages
845 - 851
Database
ISI
SICI code
0018-9383(1996)43:6<845:ECMFGL>2.0.ZU;2-J
Abstract
A simple and accurate circuit model for Heterostructure Field Effect T ransistors (HFET's) is proposed to simulate both the gate and the drai n current characteristics accounting for hot-electron effects on gate current and the effect of the gate current on the channel current, An analytical equation that describes the effective electron temperature is developed in a simple form, This equation is suitable for implement ation in circuit simulators, The model describes both the drain and ga te currents at high gate bias voltages, It has been implemented in our circuit simulator AIM-Spice, and good agreement between simulated and measured results is achieved for enhancement-mode HFET's fabricated i n different laboratories, The proposed equivalent circuit and model eq uations are applicable to other compound semiconductor FET's, i.e., Ga As MESFET's.