LOW-RESISTANCE SELF-ALIGNED TI-SILICIDE TECHNOLOGY FOR SUB-QUARTER MICRON CMOS DEVICES

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent preamorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices, 0.15-mu m CMOS devices with low-resistance and uniform TiSi2 on gate and source/drai n regions were fabricated using the SEDAM process, Non-doped silicon f ilms were selectively deposited on gate and source/drain regions to re duce suppression of silicidation due to heavily-doped As in the silico n, Silicidation was also enhanced by pre-amorphization, using ion-impl antation, on the narrow gate and source/drain regions, Low-resistance and uniform TiSi2 films were achieved on all narrow, long n(+) anti p( +) poly-Si and diffusion lagers of 0.15-mu m CMOS devices, TiSi2 films with a sheet resistance of 5 to 7 Omega/sq were stably and uniformly formed on 0.15-mu m-wide n(+) and p(+) poly-Si, No degradation in leak age characteristics was observed in pn-junctions with TiSi2 films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-mu m NMOSFET's and PMOSFET's with sell-aligned TiSi films.