AN ACCURATE GATE LENGTH EXTRACTION METHOD FOR SUB-QUARTER MICRON MOSFETS

By comparing measured and simulated gate-to-source/drain capacitances, C-gds, an accurate gate length extraction method is proposed for sub- quarter micron MOSFET's applications. We show that by including the 2- D field effect on the fringing capacitance, the polysilicon depletion and the quantum-well effects in the C-gds simulation, the polysilicon gate length, L(poly), can be accurately determined for device lengths down to the 0.1 mu m regime. The accuracy of this method approaches th at of cross-sectional TEM on the device under test, but without destro ying the device. Furthermore, we note that as a result of accurate L(p oly) extraction, the source/drain lateral diffusion length, L(diff), a nd effective channel length, L(eff), can also be determined precisely. The accuracy of L(diff) is confirmed by examining their consistency w ith experimentally obtained 2-D source/drain profile.