BUILDING-IN ESD EOS RELIABILITY FOR SUB-HALFMICRON CMOS PROCESSES/

MOSFET design in high performance CMOS technologies is driven primaril y by performance requirements and reliability issues such as hot carri er degradation. These requirements generally lead to processes that ar e inherently weak in terms of ESD and EOS. This paper presents a case of building-in ESD/EOS reliability through nMOSFET drain design for a 0.35 mu m CMOS process that compromises neither the performance nor th e hot carrier reliability. Three process options were considered: nLDD or nDDD ESD implants, and a silicide-block option. The nDDD option fo r the I/O transistors was chosen as it complied with the performance a nd reliability (ESD and HCI) specifications and its implementation cos t was lower than a silicide-block option. The paper presents data demo nstrating the advantages of the nDDD solution over the other alternati ves. Particularly, pulsed-EOS and HBM-ESD data, the impact of layout p arameters on ESD performance, and hot-carrier data are reviewed.