A REAL-TIME CLUSTERING MICROCHIP NEURAL ENGINE

This paper presents an analog current-mode VLSI implementation of an u nsupervised clustering algorithm, The clustering algorithm is based on the popular ART1 algorithm [1], but has been modified resulting in a more VLSI-friendly algorithm [2], [3] that allows a more efficient har dware implementation with Simple circuit operators, little memory requ irements, modular chip assembly capability, and higher speed figures, The chip. described in this paper implements a network that can cluste r 100 binary pixels input patterns into up to 18 different categories, Modular expansibility of the system is directly possible by assemblin g an N x M array of chips without any extra interfacing circuitry, so that the maximum number of clusters is 18 x M and the maximum number o f bits of the input pattern is N x 100, Pattern classification and lea rning is performed in 1.8 mu s, which is an equivalent computing power of 4.4 x 10(9) connections per second plus connection-updates per sec ond. The chip has been fabricated in a standard low cost 1.6 mu m doub le-metal single-poly CMOS process, has a die area of 1 cm(2), and is m ounted in a 120-pin PGA package, Although internally the chip is analo g in nature, it interfaces to the outside world through digital signal s, and thus has a true asynchronous digital behavior, Experimental chi p test results are available, obtained through digital chip test equip ment, Fault tolerance at the system level operation is demonstrated th rough the experimental testing of faulty chips.