PLANAR CLOCK ROUTING FOR HIGH-PERFORMANCE CHIP AND PACKAGE CO-DESIGN

A new concept of chip and package co-design for the clock network is p resented in this paper, We propose a two-level clock distribution sche me which partitions the clock network into two levels, First, the cloc k terminals are partitioned into a set of clusters, For each cluster, a local on-chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside this cluster, The clock signal is then distributed from the main clock driver to each of loca l buffers by means of a global clock tree, which is a planar tree with equal path lengths, With the hip chip area I/O attachment, the planar global clock tree can be put on a dedicated package layer, The interc onnect on the package layer has two to four order smaller resistance t han that on the chip layer, The main contribution of this paper is a n ovel algorithm to construct a planar clock tree with equal path length s-the length of the path from the clock source to each destination is exactly the same, In addition, the path length from the source to dest inations is minimized.