DESIGN METHODOLOGY FOR SYNTHESIZING CLOCK DISTRIBUTION NETWORKS EXPLOITING NONZERO LOCALIZED CLOCK SKEW

An integrated top-down design methodology is presented in this brief f or synthesizing high performance clock distribution networks based on application dependent localized clock skew, The methodology is divided into four phases: 1) determining an optimal clock skew schedule compo sed of a set of nonzero clock skew values and the related minimum cloc k path delays; 2) designing the topology of the clock distribution net work with delays assigned to each branch based on the circuit hierarch y, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; 3) designing circuit structures to emu late the delay values assigned to the individual branches of the clock tree: and 4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology, The clock lines are transformed from distributed resistive-capacitive interconnect lines into purely capacitive interco nnect lines by partitioning the RC interconnect lines with inverting r epeaters. Variations in process parameters are considered during the c ircuit design of the clock distribution network to guarantee a race-fr ee circuit, Nominal errors of less than 2.5% for the delay of the cloc k paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demons trated.