A. Mahmood et Wi. Baker, AN EVALUATION OF PARALLEL SYNCHRONOUS AND CONSERVATIVE ASYNCHRONOUS LOGIC-LEVEL SIMULATIONS, VLSI design, 4(2), 1996, pp. 91-105
Citations number
9
Categorie Soggetti
System Science","Engineering, Eletrical & Electronic","Computer Science Hardware & Architecture
A recent paper by Bailey [1] contains a theorem stating that the ideal
ized execution times of unit-delay, synchronous and conservative async
hronous simulations are equal under the conditions that unlimited numb
er of processors are available and the evaluation time of each logic e
lement is equal. Further it is shown that the above conditions result
in a lower bound on the execution times of both synchronous and conser
vative asynchronous simulations. Bailey's above important conclusions
are derived under a strict assumption that the inputs to a circuit rem
ain fixed during the entire simulation. We remove this limitation and,
by extending the analyses to multi-input, multi-output circuits with
an arbitrary number of input events, show that the conservative asynch
ronous simulation extracts more parallelism and executes faster than s
ynchronous simulation in general. Our conclusions are supported by a c
omparison of the idealized execution times of synchronous and conserva
tive asynchronous algorithms on ISCAS combinational and sequential ben
chmark circuits.