FABRICATION AND TESTING OF VERTICAL METAL EDGE EMITTERS WITH WELL-DEFINED GATE TO EMITTER SEPARATION

Vertical metal edge emitter arrays with well defined gate to emitter s eparations have been fabricated. The emitter to gate spacing is determ ined by the thickness of a deposited layer which can also serve as a c urrent limiting resistor. Current limiting resistors can also be forme d by a self-aligned etch of the underlying substrate. Parts with 300 n m emitter to gate spacing created using a chemical mechanical polishin g based process begin to emit at as low as 60 V. While those created u sing a reactive ion etching process with 200 nm emitter to gate spacin g begin to emit at 40 V. Emission stability is good and dc current den sities of up to 3 A/cm(2) from 100 emitter arrays on a close packed 5 mu m pitch have been demonstrated. (C) 1996 American Vacuum Society.