GENERIC DFT APPROACH FOR PATTERN SENSITIVE FAULTS IN WORD-ORIENTED MEMORIES

The testability problem of word-oriented memories (WOMs) for pattern s ensitive faults is addressed. A novel design for testability (DFT) str ategy allows efficient built-in self-testing (BIST) of WOMs. By proper selection of the memory array tiling scheme, it is possible to implem ent O(root n) BIST algorithms which test WOMs for various types of nei ghbourhood pattern sensitive faults (NPSFs). The inputs of the column decoders are modified to allow parallel writing into multiple words, a nd coincidence comparators are added to allow parallel verification of row data with minimal effect on chip area and performance.