PERFORMANCE OPTIMIZATION OF VLSI INTERCONNECT LAYOUT

This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, wit h emphasis on recent studies on interconnect design and optimization f or high-performance VLSI circuit design under the deep submicron fabri cation technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and inte rconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optim ization for highperformance interconnects, including the algorithms fo r total wire length minimization, critical path length minimization, a nd delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) high-performance clock routing, includi ng abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, non-tree clock routing , and clock schedule optimization. For each method, we discuss its eff ectiveness, its advantages and limitations, as well as its computation al efficiency. We group the related techniques according to either the ir optimization techniques or optimization objectives so that the read er can easily compare the quality and efficiency of different solution s.