A NOVEL PATH DELAY-FAULT SIMULATOR USING BINARY LOGIC

A novel path delay fault simulator for combinational logic circuits wh ich is capable of detecting both robust and nonrobust paths is present ed, Particular emphasis has been given for the use of binary logic rat her than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the al gorithm, A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test <V-1, V-2>, w hile backtracing from the POs to PIs in a depth-first manner, Rules ar e also given to find probable glitches and to determine how they propa gate through the circuit, which enables the identification of nonrobus t paths, Experimental results on several ISCAS'85 benchmark circuits d emonstrate the efficiency of the algorithm.