A METHODOLOGY FOR TESTING ARBITRARY BILATERAL BIT-LEVEL SYSTOLIC ARRAYS

In this paper, we discuss the controllability and observability issues in bilateral bit-level systolic arrays. We have introduced a new conc ept-'S-j-controllability in M steps', which is somewhat analogous to t he concept of C-testability and refers to the fact that all the cells in the array can be set to the state S-j in at most M steps after init ialization. Systolic arrays where the value of M is independent of the length. of the array are characterized. Our testing procedure is base d on partitioning the array into several identical subarrays which all ows us to apply a repetitive pattern of tests and propagate test outco me to the observable extremities so that every cell in the array is te sted by a minimum sequence of tests. Based on this concept, we have de veloped a set of sufficient conditions for an arbitrary bilateral bit- level systolic array to be testable for single faults.