DESIGN OF SI SIGE HETEROJUNCTION COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTORS/

An optimized Si/SiGe heterostructure for complementary metal-oxide-sem iconductor (CMOS) transistor operation is presented. Unlike previous p roposals, the design is planar and avoids inversion of the Si layer at the oxide interface. The design consists of a relaxed Si0.7Ge0.3 buff er, a strained Si quantum well (the electron channel), and a strained Si1-xGex (0.7 > x > 0.5) quantum well (the hole channel). The channel charge distribution is predicted using 1-D analytical model and quantu m mechanical solutions, Transport is modeled using 2-D drift-diffusion and hydrodynamic numerical simulations. An almost symmetric performan ce of p- and n-transistors with good short-channel behavior is predict ed. Simulated ring oscillators show a 4- to 6-fold reduction in power- delay product compared to bulk Si CMOS at the 0.2-mu m channel length generation.