HARDWARE FAULT LATENCY - MODEL VALIDATION

Authors
Citation
Bc. Soh et Ts. Dillon, HARDWARE FAULT LATENCY - MODEL VALIDATION, Microelectronics and reliability, 36(9), 1996, pp. 1231-1235
Citations number
5
Categorie Soggetti
Engineering, Eletrical & Electronic
ISSN journal
00262714
Volume
36
Issue
9
Year of publication
1996
Pages
1231 - 1235
Database
ISI
SICI code
0026-2714(1996)36:9<1231:HFL-MV>2.0.ZU;2-8
Abstract
A fault does not necessarily cause an immediately effective error, the reby leading to a system failure. Many experiments have shown that mos t hardware faults do not cause immediately detectable errors. In fact, it has been found that a significant proportion of the faults injecte d during the experiments remained latent, i.e. went undetected. In thi s paper we call the phenomenon the latency problem. The paper describe s an experimental study of the latency problem, with the aim of valida ting the analytical model developed by Soh and Dillon [Microelectron. Reliab. 36, 1223 (1996)]. Copyright (C) 1996 Elsevier Science Ltd.