STRUCTURALLY SELF-TESTABLE DATA-PATH SYNTHESIS OF APPLICATION-SPECIFIC INTEGRATED-CIRCUITS

Citation
Aa. Ismaeel et al., STRUCTURALLY SELF-TESTABLE DATA-PATH SYNTHESIS OF APPLICATION-SPECIFIC INTEGRATED-CIRCUITS, Computers & electrical engineering, 22(4), 1996, pp. 275-291
Citations number
11
Categorie Soggetti
Computer Application, Chemistry & Engineering","Computer Science Hardware & Architecture","Computer Science Interdisciplinary Applications","Engineering, Eletrical & Electronic
ISSN journal
00457906
Volume
22
Issue
4
Year of publication
1996
Pages
275 - 291
Database
ISI
SICI code
0045-7906(1996)22:4<275:SSDSOA>2.0.ZU;2-M
Abstract
This paper presents a technique for developing a structurally self-tes table data path from a scheduled data flow graph (SDFG). The approach is based on elimination of self adjacent registers to improve controll ability and observability of the data path, resulting in an increased level of testability. We introduce registers and functional units assi gnment graphs. We propose to interconnect the registers obtained by re gister assignment graph (RAG) with the Functional units obtained by fu nctional-unit assignment graph (FAG). The interconnection is achieved by an interconnection optimization technique. It generates a data path that is structurally self-testable. RAG eliminates resource conflicts and loop problems, whereas FAG eliminates merging of consecutive oper ations into one functional unit. The combination of RAG and FAG elimin ates the self adjacent registers. The technique is implemented on diff erent benchmark examples and the comparison results with the existing techniques are presented. It is found that our technique is more cost effective. Copyright (C) 1996 Elsevier Science Ltd