TECHNOLOGY MAPPING FOR LOW-POWER IN LOGIC SYNTHESIS

Traditionally, three metrics have been used to evaluate the quality of logic circuits - size, speed and testability. Consequently, synthesis techniques have strived to optimize for one or more of these metrics, resulting in a large body of research in optimal logic synthesis. As a consequence of this research, we have today very powerful techniques for synthesis targeting area and testability; and to a lesser extent, circuit speed. The last couple of years have seen the addition of ano ther dimension in the evaluation of circuit quality - its power requir ements. Low-power circuits are emerging as an important application do main, and synthesis for low power Is demanding attention. The research presented in this paper addresses one aspect of low-power synthesis. It focuses on the problem of mapping a technology-independent circuit to a technology-specific one, using gates from a given library, with p ower as the optimization metric. We believe that the difficulty in obt aining accurate models of power at the technology-independent level ma kes it difficult to optimize for power at this level, and thus feel th at the technology mapping step offers the most direct way of power opt imization during logic synthesis. Several issues in modeling and measu ring circuit power, as well as algorithms for technology mapping for l ow power are presented here. Empirically it is observed that a signifi cant variation in the power consumption is possible just by varying th e choice of gates selected. In fact, our experiments over a large set of benchmark circuits show that compared to mapping for power, mapping for area or delay can lead to circuits that have significantly higher power consumption: up to 32% higher in case of mapping for area, and up to 153% higher in case of mapping for delay.