AN INTEGRAL MATRIX-BASED TECHNIQUE FOR SYSTEMATIC SYSTOLIC DESIGN

In this paper we consider a systematic mapping procedure for systolic arrays. Integral matrix theory provides the basic concepts used here t o define projection and scheduling vectors. Unimodular matrices are de fined which describe projection, timing, and bases for the processor s pace and a correct timing function. The use of these matrices couples the definition of correct projection and scheduling functions and prov ides relatively simple tools for the design. The same mathematical des cription furnishes a rigorous definition of the partitioning block str ucture, as well as the cluster set. Both partitioning schemes of local ly parallel, globally sequential (LPGS) and locally sequential, global ly parallel (LSGP), as well as a number of intermediate partitioning s chemes, can be generated by using this technique. Folding (intended as spatial relocation of portions of processing elements) as well as a n umber of design constraints can also be included, and are briefly cons idered here. The possible application of a systolic design for low pow er requirements is also discussed.