An efficient solution to the generalized detailed routing problem in s
egmented channels for row-based FPGAs is presented. A generalized deta
iled routing allows routing of each connection using an arbitrary numb
er of tracks, i.e., doglegs are allowed. This approach is different fr
om the normally followed method where each connection is routed on a s
ingle straight track. We present a router that performs generalized se
gmented channel routing using a greedy approach to route channels. The
router also renders itself to limited tolerance against faults in the
routing architecture.