ZENER ZAP ANTI-FUSE TRIM IN VLSI CIRCUITS

This paper presents an overview of Zener zap anti-fuse trim as used to achieve improved accuracy in precision integrated circuits. Because t his technology spans design and manufacturing, elements of design, lay out, processing, and testing are included. The mechanism is defined an d typical applications are discussed, Layout considerations of anti-fu se devices are summarized and complex trim networks and multiplexed co ntrol methods are presented. Both bipolar and CMOS process implementat ions are considered. The paper also contains a bibliography which incl udes U.S. patents, which make up a large part of the technical documen tation of this technology.