ON THE APPLICATION OF THE NEURON MOS-TRANSISTOR PRINCIPLE FOR MODERN VLSI DESIGN

In this paper, the speed performance, power consumption, and layout ar ea of Neuron MOS transistor circuits are monitored considering the req uirements of modern VLSI design. The Neuron MOS transistor is a recent ly discovered device principle [1] which has a number of input gates t hat couple capacitively to a floating gate. The floating gate potentia l controls the current of a transistor channel. This device can be use d in logic circuits. A threshold current through the Neuron MOS transi stor can be defined that causes a switching of the output of the logic circuits as soon as the channel current surmounts or falls below the specified value. We designed two different multiplier cells, one based on a Neuron MOS inverter, and the other on a Neuron MOS n-MOSFET whic h is used as one input device of a comparator circuit. Functionality o f both cells is proven for data rates up to 50 MHz which represents th e first high-speed measurement of a circuit based on this new design p rinciple. A perspective for the upper speed limit found at more than 5 00 MHz is given by simulation. The new design principle has a layout a rea reduced by more than a factor of two compared to usual multiplier cells. Moreover, it is shown, that depending on the design chosen, hig h speed operation leads to considerable power savings. In view of thos e advantages it is concluded that the principle of threshold logic qua lifies for a major breakthrough for packing density improvement of CMO S-based applications.