A NEW DESIGN METHODOLOGY FOR 2-DIMENSIONAL LOGIC-ARRAYS

This paper introduces a new design approach that combines stages of lo gic and physical design. The logic function is synthesized and mapped to a two-dimensional array of logic cells. This array generalizes PLAs , XPLAs and cellular Maitra cascades. Each cell can be programmed to a wire, an inverter, or a two-input AND, OR or EXOR gate (with any subs et of inputs negated). The gate can take any output of four neighbor c ells and four neighbor buses as its inputs, and sends its result back to them. This two-dimensional geometrical model is well suited for bot h fine-grain FPGA realization and sea-of-gates custom ASIC layout. The comprehensive design method starts from a Boolean function, specified as SOP or ESOP, and produces a rectangularly shaped structure of (mos tly) locally connected cells. Two stages: restricted factorization, an d column folding, are discussed in more details to illustrate our gene ral methodology.