BEHAVIORAL SIMULATION AND PERFORMANCE EVALUATION OF MULTIPROCESSOR ARCHITECTURES

The development of multi-processor architectures requires extensive be havioral simulations to verify the correctness of design and to evalua te its performance. A high level language can provide maximum flexibil ity in this respect if the constructs for handling concurrent processe s and a time mapping mechanism are added. This paper describes a novel technique for emulating hardware processes involved in a parallel arc hitecture such that an object-oriented description of the design is ma intained. The communication and synchronization between hardware proce sses is handled by splitting the processes into their equivalent subpr ograms at the entry points. The proper scheduling of these subprograms is coordinated by a timing wheel which provides a time mapping mechan ism. Finally, a high level language pre-processor is proposed so that the timing wheel and the process emulation details can be made transpa rent to the user.