DESIGN AND IMPLEMENTATION OF A LOW-POWER TERNARY FULL ADDER

In this work, the design and implementation of a low power ternary ful l adder are presented in CMOS technology. In a ternary full adder desi gn, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter a nd pass transistors. In designs of PTI and NTI, W/L ratios of transist ors have been varied for their optimum performance. The ternary full a dder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an im provement by a factor of 14 and 4, respectively, and that of the NTI b y a factor of nearly 4 and 17, respectively over that of earlier desig ns implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respecti vely. The ternary full adder has been fabricated in MOSIS two micron n -well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performanc e, compared with the SPICE simulated behavior, and close agreement is observed. The ternary-valued logic circuits designed in the present wo rk which do not use depletion mode MOSFETS perform better than that im plemented earlier in DECMOS technology. The present design is fully co mpatible with the current CMOS technology uses fewer components and di ssipates power in the microwatt range.