DESIGN BASED FAILURE ANALYSIS AND YIELD IMPROVEMENT IN CMOS-CIRCUITS

In this paper we show that defect simulation is a basis for yield enha ncement strategies. These strategies involve identification of the yie ld detractors (i.e. identification of spot defect characteristics) and yield oriented layout design, which uses information about defects. I nformation about key yield detractors can be obtained in a time and co st efficient manner using defect simulation. By comparison of process variants and of SRAMs with different layouts, the sensitivity of the m ethod for process changes as well as fdr design differences is illustr ated. This leads to the conclusion that the defect and yield simulatio n tools can be used for yield oriented design. The enormous cost and t ime savings demonstrated in this work give a signal to enforce the int roduction of design based failure simulation methods into the yield le arning process.