Early failures are the dominant concern as integrated circuit technolo
gy matures into consistently producing systems of high reliability. Th
ese failures are attributed to the presence of randomly occurring defe
cts in elementary objects (contacts, vias, metal runs, gate oxides, bo
nds etc.) that result in extrinsic rather than intrinsic (wearout-rela
ted) mortality. A model relating system failure to failure at the elem
entary object level has been developed. Reliability is modelled as a f
unction of circuit architecture, mask layout, material properties, lif
e-test data, worst-case use-conditions and the processing environment.
The effects of competing failure mechanisms, and the presence of redu
ndant sub-systems are accounted for. Hierarchy is exploited in the ana
lysis, allowing large scale designs to be simulated. Experimental vali
dation of the modelling of oxide leakage related failure, based on a c
orrelation between actual failures reported for a production integrate
d circuit and Monte Carlo simulations that incorporate wafer-level tes
t results and process defect monitor data, is presented. The state of
the art in IC reliability simulation is advanced in that a methodology
that provides the capability to design-in reliability while accountin
g for early failures has been developed; applications include process
qualification, design assessment and fabrication monitoring.